正交信号发生器的FPGA设计与仿真  

Design and Simulation of Orthogonal Signal Generator Based on FPGA

作　　者：雷能芳[1] 

机构地区：[1]渭南师范学院,渭南714000

出　　处：《价值工程》2011年第24期140-141,共2页Value Engineering

基　　金：渭南师范学院重点科研计划项目(09YKF005)

摘　　要：正交信号发生器的FPGA实现通常都是基于查找表的方法,为了达到高精度要求,需要耗费大量的ROM资源去建立庞大的查找表。文中提出了一种基于流水线CORDIC算法的实现方案,可有效地节省FPGA的硬件资源。并根据DSP开发工具DSP Builder的优点,采用VHDL文本与Simulink模型图相结合的方法进行了FPGA设计,仿真结果验证了设计的正确性及可行性。The common approach to implement orthogonal signal generator on FPGA is based on look-up tables,which require a huge volume of ROM to achieve high resolution.This paper proposes a pipelined architecture for implementation of orthogonal signal generator on FPGA,which,based on CORDIC algorithm,can save considerable hardware resources and improve the speed performance as well.According to advantages of DSP Builder,the system is designed by utilizing VHDL and Simulink module.The correctness and feasibility of this design is verified by simulation result.

关 键 词：CORDIC算法 FPGA DSPBUILDER 正交信号 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]