H.264去块效应滤波器的混合递增滤波流水线设计  

Mixed increasing filter pipeline design for H.264/AVC deblocking filter

作　　者：马德[1] 黄凯[1] 陈华锋[2] 余慜[1] 严晓浪[1] 

机构地区：[1]浙江大学超大规模集成电路研究所,浙江杭州310027 [2]浙江传媒学院电子信息学院,浙江杭州310018

出　　处：《浙江大学学报（工学版）》2011年第7期1206-1214,1226,共10页Journal of Zhejiang University：Engineering Science

摘　　要：针对H.264/AVC主要档次去块效应滤波器的特点,提出一种混合递增的滤波流水线及片上存储架构.采用混合递增的去块效应滤波顺序,通过6级流水线实现像素点的并行滤波.该流水线的存储器架构可以有效支持主要档次的行/列和帧/场数据访问模式,利用滤波数据的相关性提高重用粒度,减少流水线阻塞和片外DRAM的访问.实验结果表明:与其他相关工作比较,流水线架构能够取得较好的性能和资源消耗比,在25.7K门和768ByteSRAM的硬件资源代价下,可以实现3路1080P HDTV的H.264主要档次视频实时去块效应滤波.A mixed increasing filter pipeline and its on-chip memory architecture were proposed in order to address the challenges of main-profile deblocking filter.The filter adopts mixed increasing filtering order for main-profile deblocking filter and uses six-stage pipeline for parallel filtering on target pixels.The memory architecture can efficiently support both row/column and frame/field data access in main-profile filter.Then pipeline stall and off-chip DRAM access were reduced by improving the granularity of data reusability.Experimental results show that the architecture can achieve better tradeoff between hardware cost and performance improvement compared with the related works.At the hardware cost of 25.7K gate cell and 768 Byte SRAM,three parallel real time deblocking filter for 1080P HDTV H.264 main-profile video stream can be realized.

关 键 词：去块效应滤波器 H.264/AVC 流水线 滤波 主要档次 

分 类 号：TN919.8[电子电信—通信与信息系统]