一种基于MATLAB及FPGA的FIR低通滤波器的设计与实现  

A method of design and implementation FIR digital filter by MATLAB and FPGA

作　　者：阿依夏木.力提甫 赵惠昌[2] 王丹琦[1] 

机构地区：[1]新疆师范大学物理与电子工程学院,新疆乌鲁木齐830054 [2]南京理工大学电光学院,江苏南京210094

出　　处：《电子设计工程》2011年第14期130-134,共5页Electronic Design Engineering

基　　金：国家部委基金(9140A05060209BQ0210);江苏省普通高校研究生科研创新计划项目(AD20328)

摘　　要：充分利用有限冲击响应数字滤波器(Finite Impulse Response digital filter,FIR)系数的对称特性,借助于MAT-LAB语言和现场可编程门阵列(FPGA)实现了一种高效的低通滤波器。设计过程中通过简化的VHDL语言编写程序,实现了加减乘法运算,使用优化的CSD编码技术缩短了乘法器的运算时间,采用FPGA滤波器芯片和QuartusⅡ软件搭建仿真电路、用Matlab软件进行理论验证。实验结果基本符合理论值,验证了此种滤波器的实现方法简单,计算速度快,节省硬件资源,抗干扰能力强,灵活,性能优于传统的FIR滤波器。This paper makes full use of the coefficient＇s symmetric character of the Finite Impulse Response digital filter,schemed out a sort of high efficiency low-pass filter by the means of MATLAB language and FPGA（Field Programmable Gate Arrays）.In the process of design,the addition,subtraction,and multiplication operations accomplished by using simple VHDL language,the optimized CSD（canonic signed digit） encoding technology reduced the operation time of multiplication,simulated with the FPGA chip,Quartus II software.The graphical comparison and theoretical analysis were finished by MATLAB software.The simulation results basically accord with the theoretical estimation,the outcome of the experiment shows that this technique has such advantages as simple and flexible way of design,strong anti-jamming capability,fast operation speed and economizing of devices.Its performance is much better than the conventional methods.

关 键 词：低通滤波器 有限冲激响应 现场可编程门阵列(FPGA) CSD算法 MATLAB 

分 类 号：TN431.2[电子电信—微电子学与固体电子学]