基于改进常系数乘法器的可配置2D FDCT/IDCT实现  

Implementation of 2D FDCT/IDCT using reconfigurable architecture based on improved fixed-coefficient multiplier

作　　者：徐江涛[1] 常晔 

机构地区：[1]天津大学电子信息工程学院,天津300072

出　　处：《中国科技论文在线》2011年第7期531-535,共5页

基　　金：高等学校博士学科点专项科研基金资助项目(200800561111);国家自然科学基金资助项目(60806010)

摘　　要：设计了一种基于改进常系数乘法器的可配置2D FDCT/IDCT电路结构。通过改变系数的表示方法和共用部分积节省了加法器和寄存器;通过将1D FDCT/IDCT W.H.Chen算法中并行的乘法计算转化为分时串行计算,1D FDCT和1D IDCT分别减少了15个和9个乘法器;通过FDCT与IDCT共用常系数乘法器、控制单元及转置RAM,进一步减少了硬件开销。本设计在Altera公司Cyclone EP1C12Q240C8型FPGA芯片上对该设计进行了验证,最高工作频率达149.25 MHz,与采用相同算法未进行上述改进的2D FDCT和2D IDCT结构相比,硬件开销节约了34%。An implementation of 2D FDCT/IDCT using reconfigurable architecture based on improved fixed-coefficient multiplier is presented.In order to save adders and registers,the representations of coefficients are transformed and partial products are shared by different multipliers.By transforming the parallel multiplications in W.H.Chen algorithm to serial time-sharing multiplications,15 multipliers are saved in 1D FDCT and 9 in 1D IDCT.To save the hardware cost furthermore,1D FDCT and 1D IDCT share fixed-coefficient multipliers,control unit and transposed RAM.The FPGA implementation shows that the clock rate can achieve up to 149.25 MHz,and that our design cuts down 34% of hardware cost compared with implementation of 1D FDCT and 1D IDCT using the same algorithm without improvement.

关 键 词：微电子学与固体电子学 FDCT IDCT 常系数乘法器 

分 类 号：TN919.81[电子电信—通信与信息系统]