使用DWA技术之1.2V连续时间三角积分调变器芯片设计  

Chip Design of 1.2 V Continuous-time Sigma-delta Modulator with DWA Technology

作　　者：黄进芳 林伟健[1] 刘荣宜 

机构地区：[1]国立台湾科技大学电子工程系,台湾台北10672 [2]中华电信研究所,台湾桃园32617

出　　处：《山东科技大学学报（自然科学版）》2011年第4期86-94,共9页Journal of Shandong University of Science and Technology(Natural Science)

摘　　要：设计并实现应用于WiMAX的1.2 V连续时间三角积分(Δ-Σ)调变器的芯片,该调变器主要包含主动式电阻电容(active-RC)电路、数据加权平均(DWA,data-weighted averaging)电路、回授DAC电路和四位元(4-bit)量化器,芯片设计使用TSMC 0.18μm CMOS的制程来实现。量测结果显示,在取样频率160 MHz、超取样比(OSR,oversampling ratio)为8、频宽为10 MHz时,最大的讯号杂讯比(SNR,signal-to-noise ratio)与讯号杂讯失真比(SNDR)分别为51 dB与48 dB,ENOB=7.7位元(bit),动态范围为54 dB,包含焊接垫(pads)的芯片面积为1.156(0.9×1.284)mm2,功耗仅19.8 mW。This study devoted to the chip design of a 1.2 V continuous-time sigma-delta（Δ-Σ）modulator for WiMAX applications.The proposed modulator mainly contains active-RC integrators,DWA（digital-weighted average）circuits,feedback DAC circuits,and a 4-bit quantizer and was fabricated in TSMC 0.18 um CMOS process.Measurement results showed that the chip achieved 51-dB SNR,48-dB SNDR,54-dB dynamic range and 7.7-bit ENOB at a signal bandwidth of 10 MHz and under the conditions of sampling rate of 160 MHz and OSR（oversampling ratio）of 8.The chip area including pads is 1.156（0.9×1.284）mm2 and the power consumption is 19.8 mW.

关 键 词：三角积分调变器 主动式电阻电容电路 数据加权平均电路 

分 类 号：TN792[电子电信—电路与系统]