一款结合数字校正技术的流水线ADC设计  

Design and Implementation of Digital Calibrated Pipelined ADC

作　　者：彭蓓[1] 万培元[2] 李浩[3] 黄冠中[2] 林平分[1] 

机构地区：[1]北京工业大学计算机学院,北京100124 [2]北京工业大学电控学院,北京100124 [3]中国科学技术大学物理学院,合肥230026

出　　处：《半导体技术》2011年第9期701-704,共4页Semiconductor Technology

基　　金：北京市科委基金项目(D0304004040)

摘　　要：基于65 nm CMOS工艺、1.2 V供电电压,设计了一款结合偏移双通道技术的流水线模数转换器(analog-to-digital convertor,ADC)。芯片的测试结果表明,该校正方法有效地消除和补偿了电容失配、级间增益误差和放大器谐波失真对流水线ADC综合性能的制约。流水线ADC在125 MS/s采样率、3 MHz正弦波输入信号的情况下,信噪失真比(signal-and-noise distortionratio,SNDR)从校正前的28 dB提高到61 dB,无杂散动态范围(spurious-free dynamic range,SFDR)从校正前的37 dB提高到62 dB。ADC芯片的功耗为72 mW,面积为1.56 mm2。偏移双通道数字校正技术在计算机软件上实现,数字电路在65 nm CMOS工艺、125 MHz时钟下估计得出的功耗为12 mW,面积为0.21 mm2。A digital calibrated pipelined ADC based offset split ADC calibration technique with 65 nm CMOS technology,1.2 V supply voltage was presented.The measured results indicate that the offset split ADC technique can effectively compensate for MDAC capacitor mismatch,gain mismatch and nonlinear distortion,and therefore improve the ADC performance.By employing digital calibration,the SNDR is improved from 28 dB to 61 dB,and the SFDR is improved from 37 dB to 62 dB with a 3 MHz input signal at 125 MS/S sampling rate.The ADC core consumes 72 mW,and area is 1.56 mm2.The digital calibration is implemented in PC,and the estimated power and area of this part are 12 mW and 0.21 mm2 respectively,in 65 nm CMOS technology at 125 MHz clock frequency.

关 键 词：CMOS 数字校正技术 偏移双通道技术 流水线模数转换器 信噪失真比 

分 类 号：TN792[电子电信—电路与系统]