基于AD9854的DDS+PLL的时钟源设计  

DDS+PLL design of clock source based on AD9854

作　　者：吴银标[1] 谢华[1] 付在明[1] 

机构地区：[1]电子科技大学自动化工程学院,成都611731

出　　处：《电子测量技术》2011年第8期60-62,共3页Electronic Measurement Technology

摘　　要：采用频率分段及直接数字频率合成技术和集成锁相环技术相结合的设计方法,来产生0.1 Hz^1.1 GHz连续可调的时钟信号。利用FPGA控制DDS芯片、集成锁相环芯片、可编程分频器和多路选择器,顺利实现了利用集成锁相环芯片产生GHz的时钟输出信号。测试结果表明,输出的时钟信号的频率、抖动等性能指标能够满足设计要求。利用集成锁相环芯片产生GHz的输出信号是创新。The frequency segment and direct digital frequency synthesis technology（DDS）and a combination of integrated PLL were introduced in order to produce continuously adjustable clock signal ranging between 0.1 Hz and 1.1 GHz.Using FPGA to control DDS chip,integrated PLL chip,programmable divider and multiplexer,we successfully produced GHz clock output signal in the method of using integrated PLL chip.The test results show that the frequency,jitter and other performance of output clock signal can meet our requirements.Using an integrated PLL chip to generate GHz signal is the innovation of this paper.

关 键 词：直接数字频率合成 集成锁相环 AD9854 FPGA 

分 类 号：TN743[电子电信—电路与系统]