基于FPGA的高速Viterbi译码器  

High-speed viterbi decoder based on FPGA

作　　者：牛毅[1] 马忠松[1] 

机构地区：[1]中国科学院空间应用工程与技术中心,北京100094

出　　处：《国外电子测量技术》2011年第8期63-65,共3页Foreign Electronic Measurement Technology

摘　　要：分析了卷积编码和Viterbi译码的原理,详细描述了和硬件结构对应的各个功能模块的作用和工作方式。介绍了利用FPGA内的寄存器资源采用并行处理的译码方法,达到了较高的译码速率,并且在硬件资源允许的条件下,效率还可进一步提高。The convolutional coding and Viterbi decoding principle are given, and the hardware structure and function modules corresponding to th role and working method are proposed. The parallel processing method using FPGA LUT are introduced, which can achieve high coding rate. This method could improve the efficiency if more hareware resource are allowed.

关 键 词：信道编码 FPGA 维特比译码 

分 类 号：TN791[电子电信—电路与系统]