基于CPLD的DS-SS抗干扰性能分析与设计  

Analysis and Design of Anti-jam Capability for DS_SS Based on CPLD

作　　者：马冬梅[1] 屈霞[1] 

机构地区：[1]常州大学信息科学与工程学院,江苏常州213164

出　　处：《苏州大学学报（工科版）》2011年第4期66-70,共5页Journal of Soochow University Engineering Science Edition (Bimonthly)

摘　　要：为分析扩频系统在干扰环境中的工作能力,针对纯硬件实现直接序列扩频系统(DS-SS)的复杂性,提出了一种基于CPLD的仿真方案,利用VHDL设计发端扩频和收端解扩电路,采用序列相位搜索捕获法获得同步。分别对无干扰环境、低噪声干扰和强干扰环境下系统性能进行了分析与仿真,并下载到芯片运行。仿真表明,即使干扰造成接收扩频信号中错误码元为22.9%时,系统仍能正确解扩,分析方法和结论对实际应用有一定的参考价值。To analyze the work capacity of spread-spectrum communication system under interference environment,the essence of DS-SS is studied.Aimming at the implementation complexity of DD-SS by pure hardware,a DD-SS proposal which can be applied in CPLD chip is proposed.A simulation model is established and the design of correlator and search and acpuisition by sequence phase are described in detail.The work of system under various kinds of interference is designed and analyzed.The results show that even if the spread spectrum signal has interference error code to 22.8 per cent,the system still dispread correctly.The analysis method and result have some reference value for practical applications.

关 键 词：直接序列扩频系统 相关器 序列相位搜索捕获法 抗干扰能力 

分 类 号：TN914.42[电子电信—通信与信息系统]