Single event upset induced multi-block error and its mitigation strategy for SRAM-based FPGA  

作　　者：XING KeFei YANG JianWei ZHANG ChuangSheng HE Wei 

机构地区：[1]Department of Instrument Science and Technology, School of Mechatronics and Automation, National University of Defense Technology, Changsha 410073, China

出　　处：《Science China(Technological Sciences)》2011年第10期2657-2664,共8页中国科学（技术科学英文版）

基　　金：supported by the National High Technology Research and Development Program of China ("863" Program) (Grant No. 2006SQ710375);the Civil Aerospace Technologies Advanced Research Pro-gram of China (Grant No. C1320061301);Ministries and Commissions’Advanced Research Found of China (Grant No. 9140A20070209KG0160)

摘　　要：According to the SRAM-based FPGA's single event effect problem in space application,single event upset induced multi-block error(SEU-MBE) phenomenon and its mitigation strategy are studied in the paper.After analyzing the place and route result,the paper points out that the essence of SEU-MBE is that some important modules exceed the safe internal distance.Two approaches,area constraint method(ACM) and incremental route algorithm(IRA),are proposed,which can reduce the error rate by manipulating programmable switch matrix and interconnection points within FPGA route resource.Fault injection experiments indicate that error detection rate is above 98.6% for both strategies,and FPGA resources increment and performance penalty are around 10%.

关 键 词：SRAM-based FPGA single event upset induced multi-block error place and route 

分 类 号：TP333[自动化与计算机技术—计算机系统结构] V446[自动化与计算机技术—计算机科学与技术]