基于74LS162数字钟设计及时间校准研究  

Design and digital clock time calibration based on 74LS162

作　　者：黄红飞 陈亦兵 

机构地区：[1]广东茂名广播电视大学,广东茂名525000

出　　处：《电子设计工程》2011年第17期185-187,192,共4页Electronic Design Engineering

摘　　要：数字钟电路一般设有校时功能。本文基于不截断正常的计数通路和加入校时脉冲信号对数字钟进行校时,采用了将所有计数器芯片74LS162的计数时钟输入端CP端均接同一个CP信号、将所有计数器芯片的置数端连在一起的方法。所设计的电路仅通过开关的接通或断开便可调整数字钟的时间值,而且时、分、秒的校时操作是任意的和互不干扰的。电路的设计能对秒的时间值进行调整,时钟精确度高。Digital clock circuit includes an error correction function generally. Based on the non-truncated normal counting path and adding school pulse signal on the digital clock when schooling, all the counting input CP sides of the counter chip 74LS162 are connected to a same CP signal, and all the home number sides of the encounter chips are linked together. The time value can be adjusted through turning on and off the switch of the new designed circuit and the operations among hour, minute and second are arbitrary and produce little interference. The design of the circuit enables adjustment to the value of second and improves the accuracy of the digital clock.

关 键 词：数字钟 开关 校时 置数 清零 

分 类 号：TP391.9[自动化与计算机技术—计算机应用技术]