基于Wishbone总线接口的LDPC码编码器设计  

Design of LDPC encoder based on Wishbone bus interface

作　　者：王刚[1,2] 李冰[1,2] 刘勇[2] 丁恒[1] 

机构地区：[1]东南大学集成电路学院,江苏南京210096 [2]东南大学无锡分校,江苏无锡214028

出　　处：《合肥工业大学学报（自然科学版）》2011年第9期1324-1329,共6页Journal of Hefei University of Technology：Natural Science

基　　金：国家科技支撑计划资助项目(2006BAJ05A01)

摘　　要：在传感器控制系统中,Wishbone是SOC的三大总线标准之一。文章采用可重构的方式设计了一种基于Wishbone总线的LDPC码编码器,可以运用到传感网的无线通讯中。该设计采用RU算法,减小了编码复杂度,将电路设计成流水线形式,可以根据编码器工作状态自适应地响应总线上的信号。对码率为1/2,码长为255、510和1023的信息码,其编码器电路在Xilinx Virtex2P系列FPGA上进行了验证,频率分别达到158、1601、66 MHz,增大了系统的吞吐率。Wishbone is one of System-on-Chip（SOC） bus standards which is used in sensor control system.In this paper,a reconfigurable low density parity check code（LDPC） encoder based on Wishbone standard is proposed,and it can be used in wireless communication of sensor network.The RU algorithm is applied to decreasing the encode complexity,and the pipeline structure is applied to designing the circuit.The encoder is in response to bus signal according to its working state.The decoders with a code rate of 1/2,and a message code length of 255,510 and 1 023 have been carried out in Xilinx Virtex2P series FPGA chip successfully,and the corresponding frequency is 158 MHz,160 MHz and 166 MHz.The results show that this design can increase the system throughput.

关 键 词：WISHBONE总线 可重构 低密度奇偶校验码 编码器 

分 类 号：TP336[自动化与计算机技术—计算机系统结构] TP301.6[自动化与计算机技术—计算机科学与技术]