SM3哈希算法的硬件实现与研究  

Implementation of SM3 HASH Function on FPGA

作　　者：刘宗斌[1] 马原[1] 荆继武[1] 夏鲁宁[1] 

机构地区：[1]中科院信息安全国家重点实验室,北京10049

出　　处：《信息网络安全》2011年第9期191-193,218,共4页Netinfo Security

基　　金：国家科技支撑计划2009BAH43B03支持

摘　　要：随着信息社会的进一步发展,哈希算法作为保护信息完整性的重要密码算法,它的应用越来越广泛。美国NIST组织已经顺利完成了哈希算法标准SHA0,SHA1和SHA2的征集工作,并且SHA-3的征集工作将于2012年结束。SM3作为国内商业应用中的国家标准哈希算法,于2010年12月公开。本文在硬件平台FPGA上实现了高吞吐率的SM3,经过优化处理SM3在Xilinx V5平台上的吞吐率可以达到1.5Gbps左右,并且就SM3在FPGA上的效率和SHA1,SHA2以及SHA-3的候选算法BLAKE在FPGA平台上的效率做了比较和分析。Along with the development of information network, cryptographic hash functions are used to protect information integrity and authenticity in a wide range of applications. The U.S. Institute of Standards and Technology, which already has published SHA0, SHA1 and SHA2 Algorithm, are holding a public competition to develop the future standard SHA-3 Algorithm which will be finished in 2012. This paper focused on the FPGA implementation of the SM3 Cryptographic Hash Algorithm which has been used as the commercial cipher standard of hash algorithm in China since published in December, 2010. The throughput of our proposed design on Xilinx V5 can reach to 1.5Gbps.In addition, the performance of SM3, SHA1, SHA2 and BLAKE on FPGA are also compared in the end of paper.

关 键 词：SM3 哈希函数 FPGA 

分 类 号：TN918.2[电子电信—通信与信息系统]