Hierarchical distribution network for low skew and high variation-tolerant bufferless resonant clocking  

作　　者：徐毅 陈书明 刘祥远 

机构地区：[1]School of Computer Science and Technology,National University of Defense Technology

出　　处：《Journal of Semiconductors》2011年第9期140-146,共7页半导体学报（英文版）

基　　金：Project supported by the National Science and Technology Major Project of the Ministry of Science and Technology of China(No. 2009ZX01034-001-001-006);the National Natural Science Foundation of China(No.60906014)

摘　　要：We propose a hierarchical interconnection network with two-phase bufferless resonant clock distribution, which mixes the advantages of mesh and tree architectures.The problems of skew reduction and variation-tolerance in the mixed interconnection network are studied through a pipelined multiplier under a TSMC 65 nm standard CMOS process.The post-simulation results show that the hierarchical architecture reduces more than 75% and 65%of clock skew compared with pure mesh and pure H-tree networks,respectively.The maximum skew in the proposed clock distribution is less than 7 ps under imbalanced loading and PVT variations,which is no more than 1%of the clock cycle of about 760 ps.We propose a hierarchical interconnection network with two-phase bufferless resonant clock distribution, which mixes the advantages of mesh and tree architectures.The problems of skew reduction and variation-tolerance in the mixed interconnection network are studied through a pipelined multiplier under a TSMC 65 nm standard CMOS process.The post-simulation results show that the hierarchical architecture reduces more than 75% and 65%of clock skew compared with pure mesh and pure H-tree networks,respectively.The maximum skew in the proposed clock distribution is less than 7 ps under imbalanced loading and PVT variations,which is no more than 1%of the clock cycle of about 760 ps.

关 键 词：resonant clock clock distribution network clock skew PVT variation 

分 类 号：TN47[电子电信—微电子学与固体电子学]