基于MCU的SoC芯片版图设计与验证  

Layout design and verification of SoC chip based on MCU

作　　者：王仁平[1] 何明华[1] 魏榕山[1] 

机构地区：[1]福州大学物理与信息工程学院,福建福州350108

出　　处：《福州大学学报（自然科学版）》2011年第4期539-545,共7页Journal of Fuzhou University(Natural Science Edition)

基　　金：福建省科技重大专项资助项目(2009HZ010002);福建省教育厅科研资助项目(JA09001);福建省自然科学基金资助项目(2009J05143)

摘　　要：设计应用于数字抄表系统的基于MCU的SoC芯片.芯片内部集成多个硬宏单元,采用数字和模拟分开放置的方式基于SMIC 0.18μm 1P6M工艺进行版图设计.进行等效验证、静态时序验证、后仿真和基于Virtuso环境采用Calibre工具进行的物理验证.研究和解决在版图设计和验证过程中碰到的问题.最终设计的SoC芯片满足时序和制造工艺要求.仿真验证结果达到以下指标:工作频率40 MHz,芯片面积5.014 1 mm2,功耗43.12 mW,最大电压降65.262 mV,最大地电压反弹值59.735 mV,电迁移和串扰均低于规定的阈值,通过了后仿真.An SoC chip for digital meter reading system is designed based on MCU.Multiple hard macro cells are integrated into the SoC chip.By separating the digital and analog modules,the layout is designed using SMIC 0.18μm 1P6M process.After layout design,the equivalence verification,static timing verification,post-layout simulation,and physical verification using Calibre based on Virtuso environment are carried out.The way to solve problems during layout design and verification is proposed.Finally,the SoC chip design meets the demand of timing and process.A 40 MHz working frequency,a 5.014 1 mm2 area,a 43.12 mW power dissipation,a 65.262 mV maximum voltage drop,and a 59.735 mV maximum earth rebound voltage are achieved.The electromigration and crosstalk are below threshold,and the post-layout simulation is successfully passed.

关 键 词：SOC设计 MCU 版图设计 物理验证 硬宏单元 

分 类 号：TN492[电子电信—微电子学与固体电子学]