一种精简结构的浮点蝶形运算单元设计  

Design of a Floating-point Butterfly Unit with Simplified Structure

作　　者：于龙洋[1] 段文伟[1] 李署坚[1] 

机构地区：[1]北京航空航天大学电子信息工程学院,北京100191

出　　处：《电讯技术》2011年第9期73-77,共5页Telecommunication Engineering

摘　　要：论述了一种结构精简且高效的浮点数蝶形运算单元设计,单元内部模块的使用效率接近100%。采用串行全流水线结构设计,与并行结构相比节省了75%的硬件资源消耗。利用按时间抽取(DIT)的快速傅里叶变换(FFT)算法,通过VHDL编程实现了以该蝶形单元为基础的1 024点浮点FFT处理器。QUARTUS II中的仿真结果证明了设计的正确性。该设计已成功应用于一种音频信号分析仪的信号处理部分。This paper presents an efficient design of butterfly unit with simplified structure. The occupating coefficient of inner modules of the unit is almost 100%. This unit uses a full pipeline structure, which saves 75% of the hardware resource consumption compared with the parallel structure. A floating-point FFI＂ processor based on this butterfly unit is realized by using the FFT algorithm of DIT（Decimation-in-time）. The simulation results of QUARTUS II demonstrate the correctness of the design. This design has been successfully applied in the sig- nal processing part of an audio signal analyser.

关 键 词：信号处理 蝶形运算单元 浮点数 快速傅里叶变换 流水线 按时间抽取 

分 类 号：TN911.72[电子电信—通信与信息系统]