利用改进DA算法FIR滤波器的仿真与实现  

Simulation and realization of FIR filter using modified distributed arithmetic architecture

作　　者：于亚萍[1] 刘源[1] 卫勇[1] 

机构地区：[1]天津农学院机电工程系

出　　处：《计算机工程与应用》2011年第27期77-79,118,共4页Computer Engineering and Applications

基　　金：国家星火计划项目(No.2010GA610018)

摘　　要：针对传统乘法运算在FPGA中占用大量硬件资源的弊端,根据FIR滤波器的线性特性,对串行、并行和改进的分布式算法进行研究,利用改进分布式算法在FPGA上对FIR滤波器进行设计,通过查表法完成FIR滤波器的设计,用改进分布式算法设计了16阶FIR滤波器,并在Quartus II 7.0下进行仿真,仿真结果表明,与传统方法相比,该方法能够有效减少硬件资源的使用。Aiming at the shortcoming of traditional multiplier occupying larger resource in FPGA,according to the linear characteristics of FIR filter,series Distributed Algorithm（DA）,parallel DA,and modified DA are studied.FIR filter is designed based on FPGA by modified DA.High-order FIR filter is achieved in Look-Up Table（LUT） method.16-order FIR is designed by modified DA with Quartus II 7.0.Results show that the modified method can implement FIR filters with the smaller resource usage compared with traditional methods.

关 键 词：FIR滤波器 查找表 现场可编程门阵列 分布式算法 

分 类 号：TP33[自动化与计算机技术—计算机系统结构]