A fast-locking all-digital delay-locked loop for phase/delay generation in an FPGA  

作　　者：陈柱佳 杨海钢 刘飞 王瑜 

机构地区：[1]Institute of Electronics,Chinese Academy of Sciences [2]Graduate University of the Chinese Academy of Sciences

出　　处：《Journal of Semiconductors》2011年第10期139-146,共8页半导体学报（英文版）

基　　金：Project supported by the Major National Scientific Research Plan of China(No.2011 CB933202);the National High Technology Research and Development Program of China(No.2008AA010701)

摘　　要：A fast-locking all-digital delay-locked loop（ADDLL） is proposed for the DDR SDRAM controller interface in a field programmable gate array（FPGA）.The ADDLL performs a 90°phase-shift so that the data strobe（DQS） can enlarge the data valid window in order to minimize skew.In order to further reduce the locking time and to prevent the harmonic locking problem,a time-to-digital converter（TDC） is proposed.A duty cycle corrector（DCC） is also designed in the ADDLL to adjust the output duty cycle to 50%.The ADDLL,implemented in a commercial 0.13μm CMOS process,occupies a total of 0.017 mm^2 of active area.Measurement results show that the ADDLL has an operating frequency range of 75 to 350 MHz and a total delay resolution of 15 ps.The time interval error（TIE） of the proposed circuit is 60.7 ps.A fast-locking all-digital delay-locked loop（ADDLL） is proposed for the DDR SDRAM controller interface in a field programmable gate array（FPGA）.The ADDLL performs a 90°phase-shift so that the data strobe（DQS） can enlarge the data valid window in order to minimize skew.In order to further reduce the locking time and to prevent the harmonic locking problem,a time-to-digital converter（TDC） is proposed.A duty cycle corrector（DCC） is also designed in the ADDLL to adjust the output duty cycle to 50%.The ADDLL,implemented in a commercial 0.13μm CMOS process,occupies a total of 0.017 mm^2 of active area.Measurement results show that the ADDLL has an operating frequency range of 75 to 350 MHz and a total delay resolution of 15 ps.The time interval error（TIE） of the proposed circuit is 60.7 ps.

关 键 词：all digital DLL DDR SDRAM controller time-to-digital converter duty cycle corrector DCDL FPGA 

分 类 号：TN911.8[电子电信—通信与信息系统]