基于FPGA的硬件协议栈精简实现  

Design and Implementation of Reduced Hardware Protocol Stack Based on FPGA

作　　者：胡冠敏[1] 徐志军[2] 许广杰[1] 

机构地区：[1]解放军理工大学通信工程学院研究生1队,江苏南京210007 [2]解放军理工大学通信工程学院电子信息工程系,江苏南京210007

出　　处：《军事通信技术》2011年第3期61-65,共5页Journal of Military Communications Technology

摘　　要：数据传输过程中准确性与高速性是基本的指标。针对高速网络内数据传输量大的应用需求,文章利用硬件描述语言,将TCP/IP中与UDP相关的协议栈按需精简后移植入FPGA中,通过UDP协议在硬件平台中开发网络数据传输的应用以切合大数据量的需求。在保证准确性的前提下,网络数据传输速率达到千兆网的性能。该设计使协议栈模块硬件化,易于集成在具有网络数据传输需求的系统或设备中。Accuracy and high speed are always the basic standard in data transmission. Aiming at the application of massive data transmission through high speed network, hardware behavior description language was used to transplant the reduced communication protocol stack into FPGA platform in the framework of TCP/IP. Thus the data can be transmited by UDP protocol to suit the demand of massive throughput of data. It was made possible to reach the performance of gigabit ethernet standard in the promise of accuracy. Attempt was made to get the reduced hardware protocol stack into block in this work. So it is convenient to be embeded into the devices or the ICs which need data transmission through gigabit ethernet net.

关 键 词：现场可编程门阵列 协议栈 用户数据包协议 硬件描述语言 千兆网 模块化 

分 类 号：TN919.6[电子电信—通信与信息系统]