基于FPGA数字延迟单元的实现和比较  

The implementation and comparison of DDL based on FPGA

作　　者：邱有刚[1] 黄建国[1] 李力[1] 

机构地区：[1]电子科技大学自动化工程学院,成都611731

出　　处：《电子测量技术》2011年第9期65-68,共4页Electronic Measurement Technology

摘　　要：提出了基于FPGA的数字延迟线(DDL)设计的3种方法,并分析了各自的优缺点和适用范围。在AlteraQuartus II开发平台上采用Verilog HDL语言和其自带的IP CORE分别实现了3种数字延迟线的设计,借助于QuartusⅡ集成开发环境中提供的SignalTapⅡ嵌入式逻辑分析仪进行仿真和验证,最后运用多踪示波器观察了PCB板的实际波形输出。试验结果表明,三种方法都可以实现数字延迟线,且设计相对简单,延时精度高,工作稳定可靠。This paper has proposed three methods to realize the digital delay line（DDL）based on the field programmable gates array（FPGA）and offered respective application scope.With the Verilog HDL language and its IP CORE,we have endeavored to apply these three methods.Finally we utilized the embedded logic analyzer（SignalTapⅡ）,which is provided by Quartus Ⅱ integrated development environment,to test and verify all of them.The results show that all of them are applicable and the design is comparatively simply and the module is stable and reliable.

关 键 词：数字延迟线 VERILOGHDL FPGA SignalTapⅡ 

分 类 号：TP2[自动化与计算机技术—检测技术与自动化装置]