FPGA与DDR2 SDRAM互联的信号完整性分析  

Analysis of signal integrity for interconnection between FPGA and DDR2 SDRAM

作　　者：吴长瑞[1] 岑凡[1] 蔡惠智[1] 

机构地区：[1]中国科学院声学研究所,北京100190

出　　处：《计算机工程与应用》2011年第29期158-160,共3页Computer Engineering and Applications

摘　　要：论述了Virtex-5和DDR2 SDRAM在互联中的信号完整性问题,利用前仿和后仿的措施分析和验证了它们在不同互联拓扑结构下的信号完整性。通过原型机的测试,验证了该理论在高速电路设计中的应用有效性。This paper describes the problem of signal integrity between Virtex-5 and DDR2 SDRAM interconnection.lt analyzes its signal integrity on different topologies interconnection through the method of simulation before PCB routing and after the completion of PCB routing.The result of test on prototype machine demonstrates that such theory is effective in the design of high-speed circuit.

关 键 词：信号完整性 输入输出缓冲器信息规范模型 高速印制电路板设计 HyperLynx仿真 

分 类 号：TN702[电子电信—电路与系统]