Three-dimensional global interconnect based on a design window  

作　　者：钱利波 朱樟明 杨银堂 

机构地区：[1]Microelectronics School, Xidian University

出　　处：《Chinese Physics B》2011年第10期463-468,共6页中国物理B（英文版）

基　　金：supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60676009);the Natural Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2009ZX01034-002-001-005)

摘　　要：Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit （3D IC） is predicted exactly. Using the results of this model, a global interconnect design window for a giga-scale system-on-chip （SOC） is established by evaluating the constraints of 1） wiring resource, 2） wiring bandwidth, and 3） wiring noise. In comparison to a two-dimensional integrated circuit （2D IC） in a 130-nm and 45-nm technology node, the design window expands for a 3D IC to improve the design reliability and system performance, further supporting 3D IC application in future integrated circuit design.Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit （3D IC） is predicted exactly. Using the results of this model, a global interconnect design window for a giga-scale system-on-chip （SOC） is established by evaluating the constraints of 1） wiring resource, 2） wiring bandwidth, and 3） wiring noise. In comparison to a two-dimensional integrated circuit （2D IC） in a 130-nm and 45-nm technology node, the design window expands for a 3D IC to improve the design reliability and system performance, further supporting 3D IC application in future integrated circuit design.

关 键 词：three-dimensional integrated circuit design window wiring resource bandwidth 

分 类 号：TN405[电子电信—微电子学与固体电子学]