基于FPGA的高速数据采集系统设计与实现  

Design and Implementation of High Speed Data Acquisition System Based on FPGA

作　　者：邵磊[1] 倪明[1] 

机构地区：[1]中国电子科技集团公司第三十二研究所,上海200233

出　　处：《计算机工程》2011年第19期221-223,共3页Computer Engineering

基　　金：国家部委基金资助项目

摘　　要：设计一种基于现场可编程门阵列(FPGA)的高速数据采集系统,将AT84AD001B高速A/D转换器与Stratix II系列的FPGA作为数据采集和处理主体,并在紧凑型外部设备互连系统平台上进行性能指标测试。结果表明,该系统可实现采样率为1 GS/s的双通道和采样率为2 GS/s的单通道交替并行数据采集性能,以及带宽达到200 MHz、放大倍数达到5倍的前端模拟信号调理性能,具有模块化、坚固性、可靠性和可扩展性等特点。This paper designs a high speed data acquisition system based on Field Programmable Gate Array（FPGA）.It makes AT84AD001B high-speed A/D converter and Stratix II series of FPGA as data collection and processing main body,and goes on performance index test on Compact Peripheral Component Interconnect（cPCI）.Result shows that the sampling rate is 1 GS/s dual channel and sampling rate is 2 GS/s single channel alternate parallel data acquisition performance,front analog signal conditioning performance for 200 MHz bandwidth,5 times magnification.It has the characteristics of modularization,sturdiness,high reliability and scalability.

关 键 词：现场可编程门阵列 高速数据采集 高速A/D 模拟信号调理 

分 类 号：TP39[自动化与计算机技术—计算机应用技术]