TIADC高速数据捕获和时间失配补偿的FPGA实现  

FPGA Implementation of Data Acquisition and Timing Mismatch Compensation for TIADC System

作　　者：张尚良[1] 邹月娴[1] 

机构地区：[1]北京大学现代数字信号处理实验室,深圳518055

出　　处：《数据采集与处理》2011年第5期601-608,共8页Journal of Data Acquisition and Processing

基　　金：国家自然科学基金(60775003)资助项目

摘　　要：时间交错并行采样模拟数字转换器(TIADC)模拟前端特有的多通道分时交替采样结构不可避免地引入了通道失配问题,并且给其后端多通道高速数据的捕获、缓存和处理带来了很大的设计挑战。本文针对上述技术难题,利用FPGA和SoPC技术特点,着重开展模块化TIADC通用数字后端系统设计技术研究。分别实现了对TIADC系统模拟前端多通道分时交替高速输出数据的实时捕获、多通道拉格朗日时间失配实时数字后补偿、数据的存储及传输等功能。分析表明,本文提出的数字后端系统设计方案具有良好的通用性,其模块化特性易于拓展并适用于不同的TIADC系统架构。测试结果表明本文实现的4*80MS/s12bit TIADC数字后端系统工作稳定,采用6阶拉格朗日插值滤波器使系统获得了平均25dB的SFDR性能提高。The special multichannel structure of the front-end of the time-interleaved analog-todigital converter （TIADC） introduces the channel mismatches unavoidably, and brings forth big challenges of the digital backend system design for the multi-channel high speed data capturing, processing and storing. Using the FPGA and SoPC technologies, the research focuses on the design for modular general-purpose TIADC digital backend system to overcome the above mentioned technical challenges. The digital backend system is designed to provide the functions of multichannel high-speed time-interleaved data capture, the multichannel Lagrange interpolating digital background compensation for the timing mismatch, data storage and data transmission after compensation. Analysis shows that the digital backend system proposed in this paper has well-defined characteristics of expansibility, and it can be used to design the different TIADC systems with different structures. The experimental evaluation is carried out for a designed digital backend system of a 4 ＊ 80 MS/s 12 bit TIADC system. The experimental results prove its working stability and show a 25 dB SFDR performance improvement by using the sixth order multichannel Lagrange interpolating filter.

关 键 词：时间交替并行采样 时间失配 数字后补偿 TIADC数字后端系统 

分 类 号：TP335[自动化与计算机技术—计算机系统结构]