基于脉动阵列的复数定点QR分解VLSI设计  

VLSI Design for Plural Fixed-Point QR Decomposition Based on Systolic Array

作　　者：马晓龙[1] 陈贵灿[1] 

机构地区：[1]西安交通大学电子与信息工程学院,西安710049

出　　处：《微电子学》2011年第5期685-689,共5页Microelectronics

摘　　要：提出一种应用Givens变换实现QR分解的脉动阵列中的边界单元和内部单元电路结构。在硬件成本增加不多的条件下,应用牛顿-拉夫逊迭代方法和查询表技术,实现了平方根倒数的快速计算。综合的电路工作时钟达100MHz,两种单元的数据处理周期均为120ns,阵列数据处理速度高于相关文献报道40%以上。New circuit structures of boundary cell and internal cell in systolic array were proposed,in which QR decomposition（QRD） was realized with Givens transform.Newton-Raphson iteration and look-up table were adopted to rapidly calculate inversed square root function with little extra hardware cost.The synthesized circuits operated at 100 MHz.Both cells had a data processing cycle of 120 ns,and the data processing speed of the circuit was about 40% higher than that in the published literature.

关 键 词：QR分解 脉动阵列 牛顿-拉夫逊迭代 VLSI 

分 类 号：TN47[电子电信—微电子学与固体电子学]