Low-power design and application based on CSD optimization for a fixed coefficient multiplier  

作　　者：LIU HongXia YUAN Bo 

机构地区：[1]Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Devices, School of Microelectronies, Xidian University, Xi＇an 710071, China

出　　处：《Science China(Information Sciences)》2011年第11期2443-2453,共11页中国科学（信息科学）（英文版）

基　　金：supported by the National Natural Science Foundation of China (Grant Nos. 60976068,61076097);the National Defence Advance Research Program (Grant No. 801030401);and the Fundamental Research Funds for the Central Universities (Grant No. 200807010010)

摘　　要：This paper presents a low-power design for a fixed coefficient multiplier, based on the canonic signed digit （CSD） method. The proposed technology overcomes the defects of the general CSD method by reducing system power and area substantially without additional logic. The theoretical basis and a design method are explained in detail in this paper. Our design technology was used to optimize a radio-frequency module. FPGA test results show that logic utilization is reduced by 25%, the total number of registers used is reduced by 23.02%, and the total block memory bits utilization is reduced by 20%. These results show that the proposed low-power design is an effective method.This paper presents a low-power design for a fixed coefficient multiplier, based on the canonic signed digit （CSD） method. The proposed technology overcomes the defects of the general CSD method by reducing system power and area substantially without additional logic. The theoretical basis and a design method are explained in detail in this paper. Our design technology was used to optimize a radio-frequency module. FPGA test results show that logic utilization is reduced by 25%, the total number of registers used is reduced by 23.02%, and the total block memory bits utilization is reduced by 20%. These results show that the proposed low-power design is an effective method.

关 键 词：canonic signed digit optimization coefficient of multiplication system power system area logic cell number FPGA test results 

分 类 号：TP368.1[自动化与计算机技术—计算机系统结构] O121.4[自动化与计算机技术—计算机科学与技术]