一种低功耗2.4GHz低噪声放大器设计  

Design of a Low Power 2.4 GHz LNA

作　　者：翁寅飞[1] 孙玲玲[1] 高海军[1] 林隆乾[1] 

机构地区：[1]杭州电子科技大学射频电路与系统教育部重点实验室,杭州310018

出　　处：《电子器件》2011年第5期517-520,共4页Chinese Journal of Electron Devices

基　　金：基于传输线频率选择器的CMOS硅基毫米波压控振荡器研究(KYZ043710033)

摘　　要：设计了一个低功耗2.4 GHz低噪声放大器,并详细阐述了电路的噪声匹配理论。该低噪声放大器采用经典的共源共栅结构,为了同时满足共轭匹配与噪声匹配,在输入管的栅源间增加了一个电容Cex。电路设计采用SMIC 65 nm CMOS工艺,并用Cadence进行仿真。仿真结果表明:电路在1.2 V电源电压下的功耗小于7 mW,噪声系数小于0.7 dB,增益大于21dB。电路在所需频率范围内满足绝对稳定条件,芯片版图面积为0.57 mm×0.65 mm。A 2.4 GHz CMOS low noise,low consumed power amplifier was designed,and the theories of the noise matching was presented.This amplifier was comprised of the classical cascade structure and the capacitor Cex added between the gate and the input source of MOSFET in order to meet the conjugated matching and noise matching simultaneously.The circuit is implemented with the SMIC 65nm CMOS technology and simulated by Cadence.The results show that the consumed power is less than 7 mW under the 1.2 V supply,noise figure is less than 0.7 dB and the gain is larger than 21 dB.It is unconditionally stable.The whole layout occupies 0.57 mm×0.65 mm.

关 键 词：CMOS 低噪声放大器 噪声匹配 低功耗 

分 类 号：TN4[电子电信—微电子学与固体电子学]