基于FPGA的FSO通信误码测试仪的设计  

Design of BER Tester Based on FPGA for FSO Communication

作　　者：闫思家[1] 彭仁军[1] 高建双[1] 冯波[1] 

机构地区：[1]电子科技大学光电信息学院,成都610054

出　　处：《电子器件》2011年第5期589-592,共4页Chinese Journal of Electron Devices

摘　　要：提出了一种基于FPGA的FSO通信误码测试方案。该方案中,误码测试主要是由伪随机序列发生模块、同步模块、误码统计模块以及LCD显示模块来实现,对这些模块进行了详细的论述。误码测试的关键技术之一是比特同步,该方案利用FIFO实现误码仪内部数据与接收数据之间的同步。利用该方案研制了一套10 Mbit/s的误码测试仪。大量实验表明,所研制的误码仪性能稳定可靠,证实了设计方案的可行性。目前该误码测试仪已成功应用于FSO通信系统并交付用户使用。A kind of design method for BER tester based on FPGA is put forward.In this design,BER testing includes the pseudo-random code generator module,the synchronization module,the error code statistics module and the LCD module,and the paper has discussed these modules.The synchronization is one of the key technologies in BER testing.In this design,we use FIFO to achieve the synchronization of the internal data and the received data.Using the proposed design,a 10 Mbit/s BER tester is developed.Numerous experiments have shown that the measuring system is stable and reliable,which confirmed the feasibility of the design.The BER tester has been successfully used in the FSO communication system and delivered to users.

关 键 词：FSO 误码测试 FPGA 同步 FIFO 

分 类 号：TN929.12[电子电信—通信与信息系统]