CLB总线事务级建模及其仿真平台的设计  

Transaction level modeling and the simulation platform design of CLB bus

作　　者：兰光洋[1] 魏继增[1] 郭炜[1] 

机构地区：[1]天津大学计算机科学与技术学院,天津300072

出　　处：《电子技术应用》2011年第11期134-136,共3页Application of Electronic Technique

基　　金：天津市科技支撑重点项目(08ZCGYGX00400)

摘　　要：提出了采用事务级建模的方法对国内具有自主知识产权的国芯CLB总线进行建模的方案,并利用多时钟技术来保证模型的周期精确。同时对所建模型进行了VCI接口协议的封装,便于其在不同平台上的移植。为了验证本设计的正确性,在电子系统级平台上实现了基于CLB的SoC。实验结果表明,本模型可以大大提高软、硬件协同开发验证的效率,增强IP模块的复用性。This paper using the method of TLM models the Guoxin＇s CLB bus which is authored by our own country, and multi-clock is used to confirm the cycle accurate of this model. Besides, this paper encapsulates this model with VCI protocol in order to facilitate its transplantation between different platforms. To verify the correctness of our design, this paper realized the SoC of CLB bus on electronic system level platform. The results show that this model does not only promote the efficiency of the co- design and verification of HW and SW, but also increases the reusability of the IP module.

关 键 词：systemC语言 CLB总线 IP复用 事务级建模 VCI接口 

分 类 号：TP399[自动化与计算机技术—计算机应用技术]