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出 处:《Journal of Semiconductors》2011年第11期103-109,共7页半导体学报(英文版)
基 金:supported by the Important National S&T Special Project of China(No.2009ZX01031-003-003);the NLAIC Project(No. 9140C0903091004)
摘 要:A digitally controlled pulse width modulation/pulse skip modulation (PWM/PSM) dual-mode buck DC/DC converter is proposed. Its operation mode can be automatically chosen as continuous conduction mode (CCM) or discontinuous conduction mode (DCM). The converter works in PSM at DCM and in 2 MHz PWM at CCM. Switching loss is reduced at a light load by skipping cycles. Thus high conversion efficiency is realized in a wide load current. The implementations of PWM control blocks, such as the ADC, the digital pulse width modulator (DPWM) and the loop compensator, and PSM control blocks are described in detail. The parameters of the loop compensator can be programmed for different external component values and switching frequencies, which is much more flexible than its analog rivals. The chip is manufactured in 0.13 μm CMOS technology and the chip area is 1.21 mm^2. Experimental results show that the conversion efficiency is high, being 90% at 200 mA and 67% at 20 mA. Meanwhile, the measured load step response shows that the proposed dual-mode converter has good stability.A digitally controlled pulse width modulation/pulse skip modulation (PWM/PSM) dual-mode buck DC/DC converter is proposed. Its operation mode can be automatically chosen as continuous conduction mode (CCM) or discontinuous conduction mode (DCM). The converter works in PSM at DCM and in 2 MHz PWM at CCM. Switching loss is reduced at a light load by skipping cycles. Thus high conversion efficiency is realized in a wide load current. The implementations of PWM control blocks, such as the ADC, the digital pulse width modulator (DPWM) and the loop compensator, and PSM control blocks are described in detail. The parameters of the loop compensator can be programmed for different external component values and switching frequencies, which is much more flexible than its analog rivals. The chip is manufactured in 0.13 μm CMOS technology and the chip area is 1.21 mm^2. Experimental results show that the conversion efficiency is high, being 90% at 200 mA and 67% at 20 mA. Meanwhile, the measured load step response shows that the proposed dual-mode converter has good stability.
关 键 词:digital power PSM ADC digital proportion integration differentiation DPWM BUCK
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