A 10-bit 100-MS/s CMOS pipelined folding A/D converter  

作　　者：李晓娟 杨银堂 朱樟明 

机构地区：[1]School of Microelectronics,Xidian University

出　　处：《Journal of Semiconductors》2011年第11期110-116,共7页半导体学报（英文版）

基　　金：supported by the National Natural Science Foundation of China(Nos.60725415,60971066,61006028);the National High-Tech Research and Development Program of China(No.2009AA01Z258);the National Science & Technology Important Project of China (No.2009ZX01034-002001-005)

摘　　要：This paper presents a 10-bit 100-MSample/s analog-to-digital （A/D） converter with pipelined folding architecture. The linearity is improved by using an offset cancellation technique and a resistive averaging interpolation network. Cascading alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers are used to realize the pipeline technique for obtaining high resolution. In SMIC 0.18 μm CMOS, the A/D converter is measured as follows： the peak integral nonlinearity and differential nonlin- earity are 4-0.48 LSB and 4-0.33 LSB, respectively. Input range is 1.0 Vp-p with a 2.29 mm2 active area. At 20 MHz input @ 100 MHz sample clock, 9.59 effective number of bits, 59.5 dB of the signal-to-noise-and-distortion ratio and 82.49 dB of the spurious-free dynamic range are achieved. The dissipation power is only 95 mW with a 1.8 V power supply.This paper presents a 10-bit 100-MSample/s analog-to-digital （A/D） converter with pipelined folding architecture. The linearity is improved by using an offset cancellation technique and a resistive averaging interpolation network. Cascading alleviates the wide bandwidth requirement of the folding amplifier and distributed interstage track/hold amplifiers are used to realize the pipeline technique for obtaining high resolution. In SMIC 0.18 μm CMOS, the A/D converter is measured as follows： the peak integral nonlinearity and differential nonlin- earity are 4-0.48 LSB and 4-0.33 LSB, respectively. Input range is 1.0 Vp-p with a 2.29 mm2 active area. At 20 MHz input @ 100 MHz sample clock, 9.59 effective number of bits, 59.5 dB of the signal-to-noise-and-distortion ratio and 82.49 dB of the spurious-free dynamic range are achieved. The dissipation power is only 95 mW with a 1.8 V power supply.

关 键 词：analog-to-digital converter pipelined folding resistive averaging interpolation offset cancellation 

分 类 号：TN792[电子电信—电路与系统]