Novel SEU hardened PD SOI SRAM cell  

作　　者：谢成民 王忠芳 汪西虎 吴龙胜 刘佑宝 

机构地区：[1]Computer Research & Design Department,Xi'an Microelectronic Technique Institutes

出　　处：《Journal of Semiconductors》2011年第11期162-166,共5页半导体学报（英文版）

摘　　要：A novel SEU hardened 10T PD SOI SRAM cell is proposed. By dividing each pull-up and pull-down transistor in the cross-coupled inverters into two cascaded transistors, this cell suppresses the parasitic BJT and source-drain penetration charge collection effect in PD SOI transistor which causes the SEU in PD SOI SRAM. Mixed-mode simulation shows that this novel cell completely solves the SEU, where the ion affects the single transistor. Through analysis of the upset mechanism of this novel cell, SEU performance is roughly equal to the multiple-cell upset performance of a normal 6T SOI SRAM and it is thought that the SEU performance is 17 times greater than traditional 6T SRAM in 45nm PD SOI technology node based on the tested data of the references. To achieve this, the new cell adds four transistors and has a 43.4% area overhead and performance penalty.A novel SEU hardened 10T PD SOI SRAM cell is proposed. By dividing each pull-up and pull-down transistor in the cross-coupled inverters into two cascaded transistors, this cell suppresses the parasitic BJT and source-drain penetration charge collection effect in PD SOI transistor which causes the SEU in PD SOI SRAM. Mixed-mode simulation shows that this novel cell completely solves the SEU, where the ion affects the single transistor. Through analysis of the upset mechanism of this novel cell, SEU performance is roughly equal to the multiple-cell upset performance of a normal 6T SOI SRAM and it is thought that the SEU performance is 17 times greater than traditional 6T SRAM in 45nm PD SOI technology node based on the tested data of the references. To achieve this, the new cell adds four transistors and has a 43.4% area overhead and performance penalty.

关 键 词：SEU PD SOI SRAM parasitic BJT mixed-mode simulation 

分 类 号：TN32[电子电信—物理电子学]