基于关键IP核加固的片上网络容错机制  

Fault tolerant mechanism of the network on chip with the critical IP core strengthening

作　　者：欧阳一鸣[1] 张俊威[1] 梁华国[1] 谢涛[1,2] 

机构地区：[1]合肥工业大学计算机与信息学院,合肥230009 [2]Department of Computer Science, San Diego State University, San Diego, CA 92182, USA)

出　　处：《电子测量与仪器学报》2011年第10期879-886,共8页Journal of Electronic Measurement and Instrumentation

基　　金：国家自然科学基金(编号:60876028)资助项目;安徽省自然科学基金(编号:090412034)资助项目;安徽高校省级自然科学研究重点项目(编号:KJ2010A269)资助项目

摘　　要：片上网络中的路由器故障将导致与其相连的IP核不能通信,严重影响了片上网络的性能。因此提出一种基于片上网络2D-mesh结构的容错机制,通过将关键IP核的资源网络接口与相邻节点的资源网络接口相连进行IP核的加固,在每个路由器的各个端口中配置邻居节点状态寄存器标示邻居节点的好坏,在路由计算时通过检查寄存器绕过故障路由器,同时采用拥塞机制以提高片上网络的通信效率。本文使用QuartusII软件对本文的硬件设计进行验证,使用OPNET网络仿真软件进行容错机制的验证,实验结果表明本文提出的容错机制在增加了仅2.9%的硬件开销之后可以实现关键IP核的加固,同时相比文献提出的路由算法具有较明显的优势。The fault of router in network on chip will make the IP core connected with it lose communication with others, which affects the performance of the network on chip seriously. This paper presents a fault tolerance mechanism based on 2D-mesh structure. This mechanism connects the resource network interface of the critical IP core to neighbors＇ to strengthen the critical IP core, and add a status register in each router to indicate whether the neighbor router is good or not, so in the routing calculation stage the router can make routing to bypass the fanlty routers. And at the same times the congestion mechanism is used to improve the efficiency of the communication of network on chip. Quartus II software is used to verify the electrocircuit in this paper, and OPNET software is used to test the fault tolerant mechanism. The experiment results show that the proposed mechanism can strengthen the critical IP core, and what＇s more the routers can tolerate the faults of the other routers in the case of increasing only 2.9% hardware overhead, which outperforms the other emerging alternative NoCs.

关 键 词：片上网络 容错 关键IP核 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]