基于FPGA高速数据传输的比特自校正技术  

Bit Self-revised Technique for High-speed Data Transmission Based on FPGA

作　　者：张文超[1] 黄善勇[1] 曾小东[1] 

机构地区：[1]电子科技大学电子工程学院,四川成都611731

出　　处：《无线电工程》2011年第11期19-21,共3页Radio Engineering

摘　　要：以超宽带雷达接收机实时高速信号处理为应用背景,提出了一种基于现场可编程门阵列(FPGA)的可以改善高速数据传输质量的比特自校正方案。该方案以赛灵思(Xilinx)公司Virtex-5系列FPGA为平台,通过调整每个通路内部数据的所有比特,保证每比特都在最佳时刻被采样时钟采集来克服高数据率下的静态冒险引发的逻辑错误和误码。该方案实现了320 Mbps高速数据正确传输,测试结果证明了该设计方案的可行性和稳定性。With the application of real-time high-speed signal processing in ultra-wideband radar receiver as a background,a dynamic self-revised scheme is put forward.The scheme is based on Virtex-5 series FPGA（Xinlinx corporation）,which can improve high-speed data transmission quality.It can guarantee that every bit can be sampled at the best time to conquer the logic errors and bit errors which are brought by static hazard in high data-rate condition.The scheme can realize 320Mbps high-speed data transmission and the test results confirm its feasibility and stability.

关 键 词：高速数据传输 超宽带雷达 比特自校正 FPGA 

分 类 号：TN957.5[电子电信—信号与信息处理]