一种负载为7nF片上电容的低压差线性稳压器  

A Monolithic LDO with 7 nF On-chip Load Capacitor

作　　者：龚晓寒[1] 倪金华[1,2] 洪志良[1] 刘洋 

机构地区：[1]复旦大学专用集成电路与系统国家重点实验室,上海201203 [2]亚德诺半导体技术(上海)有限公司,上海200021

出　　处：《固体电子学研究与进展》2011年第5期505-509,共5页Research & Progress of SSE

基　　金：ADI公司与复旦大学专用集成电路与系统国家重点实验室资助项目

摘　　要：详细分析并实现一种改进的片上全集成低压差线性稳压器（LDO）,其负载电容为7 nF片上电容,且在0~50 mA电流负载范围下具有很好的稳定性。电路通过电压负反馈环控制降低输出等效负载电阻,并且采用了自适应极点调节方法以确保环路的稳定性。通过快通环路和高增益环路的混合控制,既能保证高的低频增益,又能满足快速响应的要求。该LDO包括输出电容7 nF均全集成在芯片内部。经0.13μm 1P9M标准CMOS工艺流片和测试,当负载电流在0~50 mA跳变时,过冲小于90 mV,且跳变稳定,相位裕度满足要求。An improved LDO with the on-chip output capacitor of 7 nF is analyzed in details and realized to achieve good stability in various loads between 0~50 mA.The output equivalent resistance is reduced by voltage feedback loop,and the adaptive pole adjusting method is applied to guarantee the system stability.Large DC gain and fast response can be achieved by dual-loop control consisting of a fast loop and a large-gain loop.This LDO including the passive components is fully integrated on chip.The chip was implemented in a 0.13 μm standard CMOS technology.The measured overshoot is less than 90 mV when load current transients range between 0 and 50 mA.In addition,output voltage is stable during the load response,which shows a good phase margin.

关 键 词：全集成 低压差线性稳压器 自适应极点调节 快通环路 高增益环 

分 类 号：TN432[电子电信—微电子学与固体电子学] TM44[电气工程—电器]