DSP中指令Cache的低功耗设计  

Low power instruction Cache design

作　　者：杨晓刚[1] 屈凌翔[2] 张树丹[1,2] 

机构地区：[1]江南大学物联网工程学院,江苏无锡214122 [2]中国电子科技集团公司第五十八研究所,江苏无锡214035

出　　处：《计算机工程与应用》2011年第32期82-86,共5页Computer Engineering and Applications

基　　金：核高基项目(No.2009ZX01034-001-002-003)

摘　　要：设计了一种低功耗指令Cache:通过在CPU与一级指令Cache之间加入Line Buffer,来减少CPU对指令Cache的访问次数,从而降低指令Cache的功耗。此外在Line Buffer控制器中添加了重装控制单元,当指令Cache发生缺失时,能将片外存储单元中的指令直接送给CPU,从而最大限度地减少由于Cache缺失所引起CPU取指的延迟。经验证,该设计在降低功耗的同时,还提升了指令Cache的性能。This paper designs a low power instruction Cache by adding a Line Buffer between CPU and instruction Cache to reduce the on-chip cache memory access activities, consequently it decreases the energy consumption of the Cache memory.What＇s more,it also minimizes the Cache miss penalty by adding refill engine to the Line Buffer.Simulation results show that the design can not only reduce the power consumption but also improve the instruction Cache performance.

关 键 词：CACHE LINE BUFFER 低功耗 重装控制单元 

分 类 号：TP302[自动化与计算机技术—计算机系统结构]