YUV分离的两种FPGA实现  

Two Implementation Methods of YUV Separation Based on FPGA

作　　者：耿宏伟[1] 张玉璘[1] 

机构地区：[1]济南大学信息科学与工程学院,山东济南250022

出　　处：《现代电子技术》2011年第22期158-161,共4页Modern Electronics Technique

摘　　要：速度与面积的互换一直是基于FPGA设计中的一个不变的主题,在此介绍了两种YUV分离的FPGA的实现方式:基于面积的实现和基于速度的实现。前者仅用一片双口RAM串行,实现了YUV分离数据的输出;后者利用流水线的思想,基于两片双口RAM之间的乒乓操作,完成了模块的设计。通过Verilog HDL对两种方法进行了实现,并利用Mod-elSim完成了模块仿真。通过对比发现,二者各有优势:前者消耗硬件资源与面积较后者有很大改进;后者对提高整体系统实时性具有重大意义。因此,两种实现方式从两个角度为YUV的分离存储提供了可行的解决方案。The transform of speed and area is a eternal issue in the design based on FPGA.Two implementation methods（respectively based on area and speed） of YUV separation based on FPGA are introduced in this paper.The former achieves the separation data output of YUV with only a dual-port RAM,and the later fulfills the design of whole module with ping-pong operation between two dual-port RAMs by the way of pipeline.Both the two ways are implemented with Verilog HDL,and the module simulation is achieved with ModelSim.It is found by comparison that both of the two designs have their own superiorities： the former saves the hardware resources greatly,and the later improves the real-time performance of the whole system significantly.Both the two methods offer the workable measures to settle YUV separation in different views.

关 键 词：FPGA YUV分离 双口RAM 流水线 

分 类 号：TN710-34[电子电信—电路与系统]