一种三态鉴频鉴相器的设计  

A Design of Tri-state Phase-Frequency Detector

作　　者：付家喜 吴秀龙[1] 陈伟[1] 

机构地区：[1]安徽大学电子科学与技术学院

出　　处：《电子技术（上海）》2008年第12期58-60,共3页Electronic Technology

基　　金：国家自然科学基金(60576066)

摘　　要：鉴频鉴相器是电荷泵锁相环的一个重要模块,其鉴相范围、鉴相灵敏度、死区、速度等因素影响锁相环的性能。综合考虑以上因素,设计了一种三态鉴频鉴相器。该设计采用Chartered 0.35um CMOS工艺,使用Mentor公司的模拟电路仿真软件Eldo进行仿真。仿真结果表明鉴频鉴相器鉴相灵敏度好,速度快,鉴相死区仅为5ps,最大工作频率可达3GHz。该鉴频鉴相器结构简单,只用了18个管子,有效的节省了芯片面积。Phase-Frequency Detector is an important component of Charge-Pump Phase-locked Loop and some aspects of Phase-Frequency Detector affect the performance of PLL such as phase detecting range,phase sensitivity,dead zone,speed and so on.Based on these considerations,a tri-state Phase-Frequency Detector is designed.The design is based on Chartered 0.35um CMOS technology and simulated by Mentor_Eldo.The simulation results show good phase detecting character and high fast operation speed,the dead zone is only about 5ps and the max operation frequency is up to 3GHz.The Phase-Frequency Detector designed is simple in architecture and only 18 MOSFET,which saves area of chip effectively.

关 键 词：电荷泵锁相环 鉴频鉴相器 鉴相死区 鉴相灵敏度 

分 类 号：TN763.3[电子电信—电路与系统]