基于时间延迟和掩码的抗DPA方法研究  

Research of DPA Resistant Method Based on Time Delay and Masking

作　　者：王创伟[1] 张西红[1] 李永浩[1] 席伟[1] 

机构地区：[1]军械工程学院计算机工程系,河北石家庄050003

出　　处：《计算机测量与控制》2011年第11期2801-2803,共3页Computer Measurement &Control

基　　金：国家863计划项目(2007AA01Z454);国家自然科学基金项目(60940019)

摘　　要：针对时间延迟技术和掩码技术的不能完全抵御差分功耗攻击的不足,在研究差分功耗攻击防御方法的基础上,提出一种时间延迟和功耗随机化的电路结构,将其应用在AES算法中,并在FPGA开发板、示波器和PC机组成的功耗采集分析平台中进行了验证;通过DPA实验,结果表明,未加防护的AES加密算法IP核能被成功攻击,而增加时间延迟和掩码防护的AES IP核具有抗DPA攻击防护能力;文章的研究方法和思路可为功耗攻击防御研究提供一定的借鉴和参考。As the time delay can＇ t defend differential power analysis completely, the defect of the MASK technique is analyzed. Based on the protection methods for DPA, the paper propose a time delayed and power randomization circuit, AES algorithm containing this circuit is implemented and is testified in the power collection and analysis system. FPGA starter kit, and PC, oscillograph are used to construct the system. The DPA experiments can verify that the unprotected AES IP core implemented in the FPGA is successfully attacked , the masking and time delayed AES IP core has anti--DPA protection capability. The method and idea of this paper can provide certain references for re- search on power attack countermeasures.

关 键 词：差分功耗分析 FPGA AES 时间延迟 掩码 

分 类 号：TP309.7[自动化与计算机技术—计算机系统结构]