片上多核处理器排队网络建模与性能分析  

Open Queueing Network Modeling and Performance Analysis for Multi-core Processor on Chip

作　　者：郭禾[1] 刘大伟[1] 邱铁[1,2] 冯林[2] 

机构地区：[1]大连理工大学软件学院,大连116621 [2]大连理工大学创新实验学院,大连116024

出　　处：《系统仿真学报》2011年第12期2565-2570,共6页Journal of System Simulation

基　　金：国家自然科学基金(60773213)

摘　　要：设计了具有流水结构的4核处理器架构,采用基于优先级的任务服务规则,并且针对该架构建立了FPGA验证平台。利用带有阻塞和多任务等级的开环排队网络,对包含优先级调度规则的多核处理器流水结构进行了建模和性能分析。提出了一种对带有阻塞和多任务等级的开环排队网络进行近似分析的算法,对多组矩阵连乘进行了分析和建模,利用该算法得到计算结果,并且在FPGA验证平台上得到仿真结果。通过对计算结果与仿真结果性能参数的相对误差分析,表明该方法对片上多核处理器的建模和性能分析是有效的。A 4-core processor was designed with pipelines and preemptive scheduling strategy on task priority.A FPGA validation platform was also built on the architecture for the verification and test.The pipeline of multi-core processor using preemptive scheduling strategy,was modeled and analysed by open queueing network with blocking and multiple classes job.An approximate analysis algorithm was proposed,the multiplication of multi group matrix was analysed and modeled,the computation results were obtained by using this algorithm,and the simulation results were obtained by using the FPGA validation.According to the relative comparisons of performance parameters between the computation and the simulation,the method is proved to be effective for the modeling and performance analysis on the multi-core processor.

关 键 词：多核处理器 流水结构 开环排队网络 多任务等级 性能分析 

分 类 号：TP202[自动化与计算机技术—检测技术与自动化装置]