面向容错计算机的仲裁系统的设计与实现  

Design and implementation of arbitration system for fault tolerant computer

作　　者：韩建亚[1] 吴智博[1] 董剑[1] 张亚勇[1] 刘宏伟[1] 

机构地区：[1]哈尔滨工业大学计算机科学与技术系,哈尔滨150001

出　　处：《计算机应用研究》2011年第12期4554-4556,4580,共4页Application Research of Computers

基　　金：国家"863"高技术研究发展计划资助项目(2008AA01A201);国家科技部国际科技合作计划资助项目(2010DFA14400)

摘　　要：为了解决传统仲裁机制故障覆盖率和故障诊断成功率低的问题,针对容错计算机,提出了一种基于仲裁处理器的仲裁机制,并设计了仲裁系统和仲裁算法。其中仲裁处理器使用三模冗余系统和芯片级的容错设计技术,仲裁算法采用分级方式,同时采用自检测和心跳监测相结合的故障监测机制,有效地解决了单点故障和检测成功率低的问题。最后通过故障注入方式验证了仲裁系统的可用性。To greatly reduce detection costs and effectively improve scalability of system, this paper proposed an arbitration system and arbitration algorithm based on arbitration processor. Arbitration processor used TMR system and the chip level faulttolerant design technology to improve reliability. Arbitration algorithm used hierarchical mode, which could effectively reduce the arbitration overhead. With the detection and heartbeat detection, improved the fault coverage rate and the successful failure detection rate. Lastly, the reliability of the arbitration system was proved by the method of fault injection.

关 键 词：容错 仲裁 仲裁系统 三模冗余 检测机制 

分 类 号：TP302.8[自动化与计算机技术—计算机系统结构]