一种可变码长码率QC-LDPC编译码芯片设计与实现  

Design and Implementation of a Length & Rate-Variable QC-LDPC Encoding & Decoding Chip

作　　者：许仕龙[1] 李斌[1] 张晓峰[1] 

机构地区：[1]中国电子科技集团公司第五十四研究所,河北石家庄050081

出　　处：《微电子学与计算机》2011年第12期99-102,共4页Microelectronics & Computer

摘　　要：提出一种可变码长码率QC-LDPC编解码芯片结构,并进行了硬件实现,包括基于循环移位矩阵向量乘法器的编码模块和基于部分并行循环迭代译码结构的译码模块.对该QC-LDPC编解码器的性能评估结果表明:采用该结构的编解码器性能优良,实现复杂度低,数据吞吐率高.在此基础上,采用90nm CMOS工艺,对QC-LDPC编解码器进行了逻辑综合和版图设计,芯片版图面积为15mm2,功能和性能指标满足设计要求.According to the applications and requirements of QC-LDPC encoding decoding chip,a structure of length rate-variable QC-LDPC encoding decoding chip is proposed in this paper,and the hardware is implemented.An encoder based on cyclic shift matrix vector multiplier and a decoder based on partly-parallel cyclic iterative decoder structure are included in this chip.The assessment of the chip shows that the encoding decoding chip with this structure has excellent performance,low implementation complexity and high data throughput.On this basis,the QC-LDPC encoding decoding chip is conducted a logic synthesis and layout design.Layout area of the chip is 15mm2.Features and performance of the chip meet the design requirements.

关 键 词：QC-LDPC码 编译码算法 编译码结构 集成电路 

分 类 号：TN492[电子电信—微电子学与固体电子学]