In situ nanoscale refinement by highly controllable etching of the(111) silicon crystal plane and its influence on the enhanced electrical property of a silicon nanowire  

作　　者：龚宜彬 戴鹏飞 高安然 李铁 周萍 王跃林 

机构地区：[1]Science and Technology on Micro-System Laboratory,State Key Laboratory of Transducer Technology,Shanghai Institute of Microsystem and Information Technology,Chinese Academy of Sciences

出　　处：《Journal of Semiconductors》2011年第12期53-57,共5页半导体学报（英文版）

基　　金：Project supported by the State Key Development Program for Basic Research of China(No.2006CB300403);the National Hi-Tech Research and Development Program of China(No.2007AA03Z308);the Fund for Creative Research of the National Natural Science Foundation of China(No.60721004)

摘　　要：Nanoscale refinement on a （100） oriented silicon-on-insulator （SOI） wafer was introduced by using tetra-methyl-ammonium hydroxide （TMAH, 25 wt%） anisotropic silicon etchant, with temperature kept at 50 ℃ to achieve precise etching of the （111） crystal plane. Specifically for a silicon nanowire （SiNW） with oxide sidewall protection, the in situ TMAH process enabled effective size reduction in both lateral （2.3 nm/min） and vertical （1.7 nm/min） dimensions. A sub-50 nm SiNW with a length of microns with uniform triangular cross-section was achieved accordingly, yielding enhanced field effect transistor （FET） characteristics in comparison with its 100 nm- wide pre-refining counterpart, which demonstrated the feasibility of this highly controllable refinement process. Detailed examination revealed that the high surface quality of the （111） plane, as well as the bulk depletion property should be the causes of this electrical enhancement, which implies the great potential of the as-made cost-effective SiNW FET device in many fields.Nanoscale refinement on a （100） oriented silicon-on-insulator （SOI） wafer was introduced by using tetra-methyl-ammonium hydroxide （TMAH, 25 wt%） anisotropic silicon etchant, with temperature kept at 50 ℃ to achieve precise etching of the （111） crystal plane. Specifically for a silicon nanowire （SiNW） with oxide sidewall protection, the in situ TMAH process enabled effective size reduction in both lateral （2.3 nm/min） and vertical （1.7 nm/min） dimensions. A sub-50 nm SiNW with a length of microns with uniform triangular cross-section was achieved accordingly, yielding enhanced field effect transistor （FET） characteristics in comparison with its 100 nm- wide pre-refining counterpart, which demonstrated the feasibility of this highly controllable refinement process. Detailed examination revealed that the high surface quality of the （111） plane, as well as the bulk depletion property should be the causes of this electrical enhancement, which implies the great potential of the as-made cost-effective SiNW FET device in many fields.

关 键 词：TMAH etching nanofabrication silicon nanowire field effect transistor 

分 类 号：TN386.4[电子电信—物理电子学]