Continuous time sigma delta ADC design and non-idealities analysis  

作　　者：袁俊 张钊锋 吴俊 王超 陈珍海 钱文荣 杨银堂 

机构地区：[1]School of Microelectronics,Xidian University [2]Shanghai Advanced Research Institute,Chinese Academy of Sciences [3]Marvell Technology Group,Ltd.

出　　处：《Journal of Semiconductors》2011年第12期128-133,共6页半导体学报（英文版）

基　　金：Project supported by the National Science and Technology Major Projects,China(No.2010ZX03006-003-02)

摘　　要：A wide bandwidth continuous time sigma delta ADC is implemented in 130 nm CMOS. A detailed nonidealities analysis （excess loop delay, clock jitter, finite gain and GBW, comparator offset and DAC mismatch） is performed developed in Matlab/Simulink. This design is targeted for wide bandwidth applications such as video or wireless base-stations. A third-order continuous time sigma delta modulator comprises a third-order RC operational- amplifier-based loop filter and 3-bit internal quantizer operated at 512 MHz clock frequency. The sigma delta ADC achieves 60 dB SNR and 59.3 dB SNDR over a 16-MHz signal band at an OSR of 16. The power consumption of the CT sigma delta modulator is 22 mW from the 1.2-V supply.A wide bandwidth continuous time sigma delta ADC is implemented in 130 nm CMOS. A detailed nonidealities analysis （excess loop delay, clock jitter, finite gain and GBW, comparator offset and DAC mismatch） is performed developed in Matlab/Simulink. This design is targeted for wide bandwidth applications such as video or wireless base-stations. A third-order continuous time sigma delta modulator comprises a third-order RC operational- amplifier-based loop filter and 3-bit internal quantizer operated at 512 MHz clock frequency. The sigma delta ADC achieves 60 dB SNR and 59.3 dB SNDR over a 16-MHz signal band at an OSR of 16. The power consumption of the CT sigma delta modulator is 22 mW from the 1.2-V supply.

关 键 词：ADC continuous time sigma delta ADC low power design sigma delta modulation 

分 类 号：TN792[电子电信—电路与系统] TN761