A 750 MHz semi-digital clock and data recovery circuit with 10^(-12) BER  

作　　者：韦雪明 王忆文 李平 罗和平 

机构地区：[1]State Key Laboratory of Electronic Thin Films and Integrated Devices,University of Electronic Science & Technology of China

出　　处：《Journal of Semiconductors》2011年第12期139-143,共5页半导体学报（英文版）

摘　　要：A semi-digital clock and data recovery （CDR） is presented. In order to lower CDR trace jitter and decrease loop latency, an average-based phase detection algorithm is adopted and realized with a novel circuit. Implemented in a 0.13 μm standard 1PSM CMOS process, our CDR is integrated into a high speed serial and de-serial （SERDES） chip. Measurement results of the chip show that the CDR can trace the phase of the input data well and the RiMS jitter of the recovery clock in the observation pin is 122 ps at 75 MHz clock frequency, while the bit error rate of the recovery data is less than 10 × 10^-12.A semi-digital clock and data recovery （CDR） is presented. In order to lower CDR trace jitter and decrease loop latency, an average-based phase detection algorithm is adopted and realized with a novel circuit. Implemented in a 0.13 μm standard 1PSM CMOS process, our CDR is integrated into a high speed serial and de-serial （SERDES） chip. Measurement results of the chip show that the CDR can trace the phase of the input data well and the RiMS jitter of the recovery clock in the observation pin is 122 ps at 75 MHz clock frequency, while the bit error rate of the recovery data is less than 10 × 10^-12.

关 键 词：clock and data recovery INTERPOLATOR SERDES 

分 类 号：TN432[电子电信—微电子学与固体电子学]