基于Nios Ⅱ处理器的SVPWM IP Core设计  

IP Core Design of SVPWM Based on Nios Ⅱ Processor

作　　者：杜晓[1] 

机构地区：[1]盐城师范学院物理科学与电子技术学院,江苏盐城224002

出　　处：《电子科技》2011年第12期72-74,77,共4页Electronic Science and Technology

摘　　要：为降低FPGA实现3电平SVPWM算法的复杂性,减小SVPWM模块所占用的资源,文中利用正弦函数和余弦函数的关系,采用小容量ROM提出了一种新的SVPWM控制算法。利用Verilog HDL实现了算法的硬件设计,并封装成IP核以方便设计复用,在Altera公司的DE2开发板上进行了设计验证,体现了SOPC嵌入式系统的灵活性和扩展性。In order to reduce the algorithm complexity of FPGA implementation for 3-level SVPWM and the resources occupied by the SVPWM module,the paper proposes a new SVPWM control algorithm by using the small capacity ROM and the relationship between sine and cosine functions.The hardware design of the algorithm is implemented by using Verilog HDL,and packaged into IP cores to facilitate design reuse.The design is tested and verified by Altera’s DE2 board,which shows the flexibility and expandability of the SOPC embedded system

关 键 词：有源逆变 SVPWM IP CORE SOPC 

分 类 号：TP271.5[自动化与计算机技术—检测技术与自动化装置]