A LOW POWER TIME-TO-DIGITAL CONVERTER FOR ALL-DIGITAL PHASE-LOCKED LOOP  

作　　者：Yu Guangming Wang Yu Yang Huazhong 

机构地区：[1]Department of Electronic Engineering, Tsinghua National Laboratory for Information Science and Technology （ TNList）, Tsinghua University, Beijing 100084, China

出　　处：《Journal of Electronics(China)》2011年第3期402-408,共7页电子科学学刊（英文版）

基　　金：Supported by the Tsinghua National Laboratory for Information Science and Technology(TNList)Cross-Discipline Foundation;the National Science and Technology Major Project(No.2010ZX03006-003-01)

摘　　要：Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.Time-to-Digital Converter （TDC） is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop （ADPLL）. Usually, it occupies a large proportion of ADPLL＇s total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block （PMB） is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.

关 键 词：Low power Power management All-Digital Phase-Locked Loop (ADPLL) Time-to-Digital Converter (TDC) 

分 类 号：TN911.8[电子电信—通信与信息系统]