数字控制振荡器的设计和顶层模型  

Design and Modeling of Digitally Controlled Oscillator

作　　者：田欢欢[1] 刘振宇[1] 谢小娟[1] 李志强[1] 吴茹菲[1] 张海英[1] 

机构地区：[1]中国科学院微电子研究所,北京100029

出　　处：《微电子学》2011年第6期775-779,共5页Microelectronics

基　　金：国家自然科学基金资助项目(60276021);国家重点基础研究发展计划资助项目(G2002CB311901)

摘　　要：采用0.18μm CMOS六层金属工艺,利用带中心抽头的对称螺旋电感和新型电容调谐阵列构成的LC谐振回路,设计并实现了一种低功耗低相位噪声的数字控制振荡器(DCO)。流片测试结果表明,相位噪声在1MHz偏移频率处为-119.77dBc/Hz。电路采用1.8V电源供电,消耗约4.9mA电流,当电源电压降到1.6V时,消耗约4.1mA的核心电路电流,此时,相位噪声在1MHz频偏处仍达到-119.1dBc/Hz。为了提高全数字锁相环设计效率,采用硬件描述语言,构建了一种适用于全数字锁相环的仿真模型。该模型能大大缩短早期系统级架构选择和算法级行为验证的时间。A monolithic low-power and low-phase-noise digitally controlled oscillator（DCO） based on symmetric spiral inductor with center-tap and novel capacitor bank was implemented in 0.18 μm CMOS process with six metal layers.A new way to change capacitance was proposed and implemented.Test results showed that the circuit had a phase noise below-119.77 dBc/Hz at 1 MHz offset frequency,while drawing only 4.9 mA of current from 1.8 V supply.Also,the DCO could operate at low supply voltage with 1.6 V power supply and 4.1 mA supply current for its core circuit,achieving a phase-noise of-119.1 dBc/Hz at 1 MHz offset.In addition,a simulation model for ADPLL（all-digital phase-locked loop） was built based on hardware description language,which greatly shortened the time spent on system-level architecture and algorithm-level behavior verification.

关 键 词：数字控制振荡器 LC谐振 LC振荡器 仿真模型 

分 类 号：TN432[电子电信—微电子学与固体电子学]