基于FPGA的AES算法的实现  

Implementation of AES Algorithm based on FPGA

作　　者：梁旭 凌朝东[1,2] 张丽红[2] 

机构地区：[1]厦门市集成电路设计公共服务平台,福建厦门361008 [2]厦门市专用集成电路系统重点实验室,福建厦门361008

出　　处：《通信技术》2011年第12期111-113,116,共4页Communications Technology

基　　金：福建省科技计划项目(No.2011H6018)

摘　　要：介绍了高级加密标准(AES,Advanced Encryption Standard)算法的原理,设计了一个能够实现初始密钥128位、192位和256位可选的AES加解密算法系统,以适应多种使用环境。实验结果表明了基于现场可编程门阵列(FPGA)可编程逻辑器件的实现方法提供了并行处理能力,达到设计所要求的处理性能基准。整个设计具有很强的实用性,运行稳定,且效果良好,可以被广泛应用于网络,文件等安全系统。The principle of AES algorithm is described, and for adaptation to various environments, an AES encryption/decryption algorithm system capable to optionally implement the initial key 128, 192 or 256 is designed. The experimental results show that the implementation based on FPGA could provide parallel processing capabilities, and meet the design requirements of benchmark processing performance. With great practicability, stability and good performance, this design could be applied in security systems of network, files, ect.

关 键 词：高级加密标准算法 加密 解密 密钥 现场可编程门阵列 

分 类 号：TP309[自动化与计算机技术—计算机系统结构]