一种改进的对抗软错误电路结构设计  

Design of EDAC Circuit Structure Depending on Clock Edge

作　　者：聂永峰[1] 于东英[1] 曾泽嵘[1] 甘智勇[1] 陈梦远[1] 

机构地区：[1]电子科技大学,四川成都610054

出　　处：《现代电子技术》2011年第24期184-187,共4页Modern Electronics Technique

摘　　要：给出了一种改进的基于时钟沿的自我检测和纠正的电路结构,以纠正由单粒子翻转(SEU)引起的数据错误。简单概述了已有的检测和纠正SEU的电路结构,并在该电路的基础上提出了改进的电路结构,以实现对触发器以及SRAM等存储器的实时监控,并可以及时纠正其由于SEU引起的数据错误。采用内建命令进行错误注入模拟单粒子翻转对电路的影响。改进的电路与原来的电路相比,以微小的面积和较少的资源换取更高的纠错率。An improved EDAC circuit structure depending on clock edge is presented to correct the error caused by SEU.The existing EDAC circuit structure is briefly outlined.An improved circuit structure is proposed on the basis of this circuit to implement the real-time monitoring of FF,SRAM and other memorizers,and correct the data errors caused by SEU on time.The built-in instruction is adopted to conduct the fault inject for simulating the effect of SEU on the circuit.The improved circuit achieved equal correction rate at the cost of smaller area and fewer resources,compared with the original circuit.

关 键 词：SEU 检测和纠正 时钟沿 FPGA 触发器 

分 类 号：TN710-34[电子电信—电路与系统]